1. Field of the Invention
The present invention relates to a bonding pad structure in a semiconductor device, and more particularly, to a bonding pad structure capable of lowering the effective capacitance between a bonding wire and substrate.
2. Description of the Prior Art
Microchips (or chips) are common components in various electronic devices nowadays. In general, bonding pads must be disposed on a chip to allow external bonding wires to be electrically connected to a core circuit of the chip. The core circuit of the chip can transmit output signals to an external circuit or receive input signals transmitted from the external circuit through the bonding pads. In conventional semiconductor processes, a plurality of metal layers are utilized as main structures of the bonding pads in order to avoid a peel-off effect, and to ensure reliability of the bonding pads.
However, in the conventional bonding pad structure, there exists a parasitic capacitance between any two adjacent metal layers. There also exists a parasitic capacitance between the bottom metal layer and the substrate of the chip. The parasitic capacitances contribute equally to the effective capacitances of the connecting bonding wires to the substrate. Since effective capacitances exist between the bonding wires and the substrate, there will be signal loss to the substrate due to the effective capacitances of the bonding pads during operation of the external circuit transmitting signals to the core circuit through the bonding wires and the bonding pads. Signal loss will also result from operation of the core circuit when transmitting signals to the external circuit through the bonding pads and the bonding wires. Furthermore, the effective capacitances of the bonding pads will also lower noise immunity of the bonding pads against the substrate, and therefore increase the noise figure. All of these negative effects will reduce optimal performance of the chip, especially for high speed device applications where these defects will be more obvious.